COA Master Cheatsheet

Cheatsheet Content

### Legend * ✏️ **DIAGRAM**: Draw for marks * 🖊️ **WRITE**: What to type/write (bullets) * ⭐: Highest scoring ### Digital Logic & System Basics #### Combinational Logic ##### ⭐ Full Adder * ✏️ XOR→X; XOR(X,Cin)=SUM; Carry: 3 AND → OR * 🖊️ S=A⊕B⊕Cin; Cout=AB+ACin+BCin + Truth table ##### ⭐ Full Subtractor * ✏️ **2 Half-Sub + OR** (B1,B2 → OR = Bout) * 🖊️ D=A⊕B⊕Bin; Bout=(A'B)+Bin·(A⊕B)' + Truth table #### Sequential Logic ##### JK Flip-Flop * ✏️ JK symbol (J,K,CLK▶️,Q,Q’) * 🖊️ Table + Eqn: Qn+1=JQ’+K’Q ##### ⭐ Counters (Sync vs Async) * ✏️ Sync: common CLK to all FF | Async: ripple Q0→CLK1→CLK2 * 🖊️ Compare: delay, speed, hardware ### ISA & Processor #### Register Transfer + Bus System * ✏️ Common BUS with registers + control unit (enable/load) * 🖊️ Tri-state (0/1/Z), bus contention point #### Instruction Cycle * ✏️ CPU datapath: PC→MAR→MEM→MDR→IR→CU→ALU * 🖊️ Fetch RTN (underline): MAR←PC; MDR←M[MAR]; IR←MDR; PC←PC+1 #### Addressing Modes (4 must) * ✏️ (No diagram) * 🖊️ Immediate / Direct / Indirect (2 memory access) / Relative (EA=PC+off) + 1 example each ### Memory Organization #### Memory Hierarchy * ✏️ Pyramid: Registers→Cache→RAM→SSD/HDD * 🖊️ Speed high→low; capacity low→high #### Locality of Reference * ✏️ Optional mini box * 🖊️ Temporal + Spatial + loop example #### Cache Organization (MOST IMPORTANT) ##### ⭐ Mapping Techniques * ✏️ Direct: block→fixed line + TAG|LINE|OFFSET * ✏️ Assoc: “any line” + tag compare all * ✏️ Set-Assoc: sets (2-way) + block→set * 🖊️ Compare table cost/speed/miss ##### ⭐ Hit/Miss + AAT * ✏️ (No diagram) * 🖊️ HR, MR=1−HR; **AAT=HR×Hit + MR×MissPenalty** (1 solved numeric) ##### Write Policies (extra scoring) * ✏️ Write-through vs Write-back + dirty bit * 🖊️ Compare table ##### Cache Levels * ✏️ CPU↔️L1↔️L2↔️L3↔️RAM * 🖊️ L1 fastest small, L3 shared large ### Computer Arithmetic #### Number Representation ##### Signed vs Unsigned * ✏️ (No diagram) * 🖊️ Range note + 2’s complement meaning (1 short example) ##### ⭐ Overflow detection * ✏️ Rule box * 🖊️ ++→− and −−→+ ; Carry-in MSB ≠ Carry-out MSB #### 2) ⭐ Booth Algorithm (SIGNED MULTIPLICATION) * ✏️ Booth **step table** (A,Q,Q−1,M,ARS) * 🖊️ Rule: 01 add, 10 sub, 00/11 nop + ARS + Final=(AQ) #### Floating Point (IEEE-754) * ✏️ 32-bit box: Sign(1)|Exp(8)|Mant(23) + Bias=127 * 🖊️ Steps: normalize→exponent bias→mantissa ##### Floating point add/sub (basic) * ✏️ Flow: align exp→add/sub mantissa→normalize→round * 🖊️ 5 steps only ### I/O Organization #### ⭐ DMA * ✏️ CPU→DMA↔️I/O ; DMA↔️Memory * 🖊️ init→bus req→grant→transfer→interrupt + advantage #### ⭐ Interrupt Cycle * ✏️ Flowchart: finish→save PC/flags→ISR→restore→resume * 🖊️ Keywords: ISR, vector, context #### I/O Mapping * ✏️ Address space diagram: memory-mapped (shared) vs isolated (separate) * 🖊️ LOAD/STORE vs IN/OUT + compare table #### I/O Data Transfer Methods * ✏️ (No diagram) * 🖊️ Compare table: Programmed vs Interrupt vs DMA (CPU overhead/throughput/best use) ### ⭐ Top Exam Diagram Priority (must practice 5–7 times each) 1. Full Adder 2. Full Subtractor (2 half-sub) 3. Sync vs Async counter 4. CPU Datapath (PC/MAR/MDR/IR) 5. Cache mapping (Direct + Tag/Line/Offset) 6. Set-associative sets 7. Booth step table 8. DMA block diagram 9. Interrupt flowchart 10. IEEE 754 box ### ✅ Ultra-Compact Final Recall (covers whole syllabus) #### CPU/ISA * **Fetch RTN:** MAR←PC; MDR←M[MAR]; IR←MDR; PC←PC+1 * **Addressing modes:** Immediate | Direct | Indirect(2 mem) | Relative(EA=PC+off) * **Bus:** one source on bus at a time (tri-state Z) + enable/load #### Memory/Cache * **Hierarchy:** Reg→Cache→RAM→Disk; **Locality:** Temporal + Spatial * **Direct map:** Line=Block mod Lines; Addr=Tag|Line|Offset * **Assoc:** any line (tag compare all) | **Set-assoc:** block→set then any line * **AAT:** HR, MR=1−HR; AAT=HR×Hit + MR×MissPenalty * **Write:** WT (update RAM) vs WB (dirty bit, update later) * **Levels:** L1 fastest/small; L3 largest/shared #### Arithmetic * **2’s comp overflow:** ++→−, −−→+; Cin(MSB)≠Cout(MSB) * **Booth:** Q0Q−1: 01 add, 10 sub, 00/11 nop + ARS; Product=(AQ) * **IEEE-754 (32b):** S1|E8(bias127)|M23; FP add/sub: align exp→±mantissa→normalize→round #### I/O * **DMA:** init→bus req→grant→block transfer→interrupt * **Interrupt cycle:** finish instr→save PC/flags→ISR→restore→resume * **I/O mapping:** Memory-mapped (LOAD/STORE, shared space) vs Isolated (IN/OUT) * **Transfer methods:** Programmed(polling) vs Interrupt vs DMA (best throug