Output: Continuous square/pulse train.

Trigger: Self-triggered (no external input).

Uses: Clock/pulse generation, tone generation.

Example: 555 astable for clock.

Stable States: One stable state, one quasi-stable state.
Output: Single pulse per trigger.
Trigger: Requires external trigger to start pulse.
Uses: Timers, missing-pulse detection, one-shot timing.
Example: 555 monostable for one-shot delay.
Working Principle:
- Assumes output $V_o = +V_{sat}$ (stable state). Diode $D_1$ clamps capacitor voltage to $0.7V$.
- Negative trigger $V_T$ applied to non-inverting input $\to$ effective voltage less than $0.7V$.
- Output switches to $-V_{sat}$ (quasi-stable state). Diode $D_1$ reverse biased, capacitor charges exponentially towards $-V_{sat}$.
- When capacitor voltage reaches $- \beta V_{sat}$, output switches back to $+V_{sat}$.
- Capacitor discharges, returns to $0.7V$.

Definition: Converts digital word into analog output using resistors weighted according to powers of two ($R, 2R, 4R, \dots$).
Working Principle: Each digital bit controls a switch, current contribution from each resistor is summed, output voltage proportional to digital input.
Resolution: Smallest change in analog output for a one-bit change in input. $Resolution = \frac{V_{ref}}{2^n-1}$.
Advantage: Simple concept.
Limitation: Requires wide range of precise resistor values, difficult to fabricate accurately for high resolution.

Definition: Converts digital word into analog output using only two resistor values ($R$ and $2R$) in a ladder network.
Advantage: Requires only two resistor values, easier to fabricate accurately (better matching $\to$ improved linearity), easier IC implementation.
Limitation: Slightly slower due to ladder network and switching delays.

Operating Principle: Uses a resistor ladder to generate reference voltages and compares input simultaneously with all reference levels using comparators.
Speed: Fastest ADC architecture because entire conversion happens in one step, no clock cycles needed for conversion.
Comparators: For $n$-bit ADC, $2^n-1$ comparators are needed.
Conversion Delay: Time required for comparators to respond.

Definition: Converts analog input by comparing it with outputs from an internal DAC using a binary search algorithm.
Key Advantage: Excellent balance between speed and accuracy. Faster than integrating ADCs, more accurate than flash ADCs.
Building Blocks: Sample and Hold circuit, Comparator, SAR, Digital-to-Analog Converter (DAC).

Advantages (precision measurement):
- High accuracy and excellent noise rejection.
- Insensitive to component variations (R, C stability).

Definition: Oscillator whose output frequency varies linearly with an applied control voltage.
Output Frequency: $f_o = f_{free} + K_v V_c$ (where $f_{free}$ is free-running frequency, $K_v$ is frequency sensitivity, $V_c$ is control