Analog and Digital Integrated Circuits F

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Operational Amplifier Formulas Inverting Op-Amp Gain: $A_v = -\frac{R_f}{R_1}$ Non-Inverting Op-Amp Gain: $A_v = 1 + \frac{R_f}{R_1}$ Op-Amp Differentiator: $V_o = -RC \frac{dV_{in}}{dt}$ Op-Amp Integrator: $V_o = -\frac{1}{RC} \int V_{in} dt$ CMRR (Common Mode Rejection Ratio): $CMRR = \frac{A_d}{A_{cm}}$ Gain-Bandwidth Product (GBW): $A_v \times f = \text{constant}$ Slew Rate (SR): $SR = \frac{dV_o}{dt}$ Low-Pass Filter Cutoff Frequency: $f_c = \frac{1}{2\pi RC}$ High-Pass Filter Cutoff Frequency: $f_c = \frac{1}{2\pi RC}$ Band-Pass Filter Center Frequency: $f_c = \sqrt{f_L f_H}$ Digital-to-Analog Converters (DAC) DAC Resolution: $\text{Resolution} = \frac{V_{ref}}{2^n - 1}$ Weighted-Resistor DAC Output (n-bit): $V_{out} = V_{ref} \left( \frac{b_{n-1}}{2^0} + \frac{b_{n-2}}{2^1} + \dots + \frac{b_0}{2^{n-1}} \right)$ R-2R Ladder DAC Output (n-bit): $V_{out} = V_{ref} \sum_{i=0}^{n-1} b_i 2^{i-n}$ Analog-to-Digital Converters (ADC) Flash ADC Comparators (n-bit): $2^n - 1$ comparators Voltage-Controlled Oscillator (VCO) Frequency: $f_o = f_{free} + K_v V_c$ VCO Frequency Sensitivity: $K_v = \frac{\Delta f_o}{\Delta V_c}$ Phase-Locked Loop (PLL) Free-Running Frequency (565 PLL): $f_o = \frac{1.1}{R_1 C_1}$ Lock Range (565 PLL): $f_L = \pm \frac{8 f_o}{V_{CC}}$ Capture Range (565 PLL): $f_C \approx \frac{f_L}{\sqrt{2}}$ Loop Filter Cutoff Frequency: $f_c = \frac{1}{2\pi R_2 C_2}$ Frequency Synthesizer Output: $f_{VCO} = \left(\frac{N}{M}\right) f_{OSC}$ Boolean Algebra & Logic Gates De Morgan's Theorems: $(A \cdot B)' = A' + B'$ $(A + B)' = A' \cdot B'$ Half Adder: Sum: $S = A \oplus B$ Carry: $C = A \cdot B$ Full Adder: Sum: $S = A \oplus B \oplus C_{in}$ Carry Out: $C_{out} = AB + BC_{in} + AC_{in}$ Half Subtractor: Difference: $D = A \oplus B$ Borrow Out: $B_{out} = A' \cdot B$ Full Subtractor: Difference: $D = A \oplus B \oplus B_{in}$ Borrow Out: $B_{out} = A'B + A'B_{in} + BB_{in}$ 1-bit Digital Comparator (Equality): $E = A \odot B = AB + A'B'$ Decoder (n-to-$2^n$): Each output $Y_i$ corresponds to one minterm. Encoder (2^n-to-n): Output is binary code of active input. Priority Encoder (8-to-3): $A_2 = Y_7 + Y_6 + Y_5 + Y_4$ $A_1 = Y_7 + Y_6 + Y_3 + Y_2$ $A_0 = Y_7 + Y_5 + Y_3 + Y_1$ Flip-Flops & Sequential Circuits SR Flip-Flop Characteristic Equation: $Q_{n+1} = S + R'Q_n$ (valid for $SR=0$) D Flip-Flop Characteristic Equation: $Q_{n+1} = D$ JK Flip-Flop Characteristic Equation: $Q_{n+1} = JQ_n' + K'Q_n$ T Flip-Flop Characteristic Equation: $Q_{n+1} = T \oplus Q_n = TQ_n' + T'Q_n$ Counter (n flip-flops): Max Count = $2^n - 1$ Minimum Flip-Flops for N states: $2^n \ge N$