Semiconductor Packaging & FA

Cheatsheet Content

### Semiconductor Packaging & Assembly Fundamentals #### What is Semiconductor Packaging? Process of enclosing an IC chip (die) into a protective case and providing electrical connections. - **Key Steps:** Dicing (separating chips), Mounting (on substrate), Electrical Connection (wire bonding/flip-chip), Encapsulation (protective material). - **Why Needed?** Electrical interconnection, Mechanical protection, Environmental protection, Heat dissipation, Electrical performance, Handling & Integration, Reliability & Testing. #### Major Components of an IC Package - **Semiconductor Die (Chip):** Core electronic circuit. - **Die Attach:** Fixes die to substrate, provides mechanical support & heat conduction. - **Lead Frame / Substrate:** Mechanical base, electrical pathways. - **Bond Wires / Interconnects:** Connects die pads to package leads (e.g., Au, Al, Cu wires). - **Encapsulation:** Protective material (plastic/ceramic) covering internal components. - **External Leads / Pins / Solder Balls:** Connects IC to PCB. - **Heat Sink / Thermal Pad:** Dissipates heat. #### IC Package Assembly Process Flow (Sequential) 1. **Wafer Dicing:** Wafer cut into individual dies. 2. **Die Attach:** Die mounted on lead frame/substrate. 3. **Wire Bonding / Interconnection:** Wires connect die pads to package leads. 4. **Encapsulation (Molding):** Assembly sealed in plastic/ceramic. 5. **Curing:** Mold compound hardened by heat. 6. **Trimming & Forming:** Excess metal removed, leads shaped. 7. **Marking:** Package labeled (IC name, number, logo). 8. **Testing:** IC tested for functionality & defects. #### Wafer Map - **Definition:** Graphical representation of dies on a wafer, showing test results (good/bad/defective). - **Purpose:** Identify usable dies, improve yield, detect defect patterns, guide die picking. - **Types of Bins:** Good dies (Bin 1), minor defects (Bin 2+), non-functional (Reject bin). #### Die Attach Process (Sequential Steps) 1. **Wafer Mounting & Die Preparation:** Wafer mounted on tape. 2. **Die Picking:** Individual die picked using vacuum tool. 3. **Adhesive Application:** Epoxy/solder/film applied to die pad. 4. **Die Placement:** Die accurately placed on adhesive. 5. **Alignment:** Proper orientation for bonding. 6. **Bonding / Fixing:** Light pressure for contact/adhesion. 7. **Curing / Reflow:** Adhesive cured (epoxy) or melted (solder) to form bond. 8. **Cleaning:** Remove excess material. 9. **Inspection:** Check for voids, misalignment, tilt, adhesion. - **One-line Flow:** Die Pick → Adhesive Apply → Placement → Alignment → Bonding → Curing/Reflow → Inspection ### Advanced Interconnects & Encapsulation #### Wire Bonding - **Definition:** Thin metallic wire forms electrical connection between IC die bond pads and substrate/leadframe terminals. - **Materials:** Gold (Au), Copper (Cu), Aluminum (Al), Silver (Ag), Hybrid Wires. - **Requirements for Good Wire:** High electrical/thermal conductivity, high mechanical strength, corrosion resistance, good bondability, high fatigue resistance. - **Reliability Issues:** Wire sweep, Bond lift, IMC brittleness, Kirkendall voids, Corrosion. #### Wire Bonding Methods 1. **Thermocompression Bonding:** Oldest method, uses heat ($>300^\circ C$) + pressure for solid-state bond (Gold-to-gold). 2. **Ultrasonic Bonding:** Uses ultrasonic vibration + pressure (no external heat) for Al & Cu wires. 3. **Thermosonic Bonding:** Most common modern method, combines moderate heat + ultrasonic vibration + pressure. - **Ball Bonding vs. Wedge Bonding:** Ball bonding (Au/Cu, faster, higher loop) uses EFO to form a ball; Wedge bonding (Al, finer pitch, slower) uses wedge-shaped tool. #### Flip Chip Process Steps (Sequential) 1. **Wafer Bumping:** Solder bumps formed on die pads. 2. **Wafer Dicing:** Bumped wafer cut into dies. 3. **Flux Application:** Flux removes oxides, improves wetting. 4. **Die Pick and Flip:** Die picked and flipped upside down. 5. **Alignment:** Die bumps aligned with substrate pads. 6. **Placement:** Die placed with controlled pressure. 7. **Reflow Soldering:** Heat melts solder bumps, forms electrical/mechanical connections. 8. **Cleaning:** Removes flux residues. 9. **Underfill Dispensing:** Epoxy underfill injected between die and substrate (improves mechanical strength, thermal cycling reliability). 10. **Curing:** Underfill hardened by heat. 11. **Inspection & Testing:** Checks alignment, connections, functionality. - **One-line Flow:** Bumping → Dicing → Flux → Flip & Align → Placement → Reflow → Cleaning → Underfill → Curing → Testing - **Advantages:** Very high I/O density, very short electrical path, excellent high-speed/thermal performance, smaller package size. - **Disadvantages:** Higher manufacturing cost, CTE mismatch issues, underfill requirement, difficult rework. #### Reflow Process & Solder Joint Formation - **Definition:** Thermal process where solder bumps are heated above melting temperature to form electrical/mechanical joints. - **Steps (Thermal Profile Stages):** 1. **Preheat Stage:** Gradual temp increase ($ \approx 150^\circ C$), removes moisture, prevents thermal shock. 2. **Soak Stage:** Temp held ($ \approx 150-180^\circ C$), activates flux, ensures uniform heating. 3. **Reflow Stage:** Temp above solder melting point ($ \approx 220-260^\circ C$), solder melts and wets pads. 4. **Cooling Stage:** Controlled cooling to solidify solder, forms strong joints. - **Solder Joint Formation Mechanism:** Melting → Wetting → Intermetallic Compound (IMC) Formation → Solidification. - **Key Points:** Proper temperature profile is critical. Too high/low causes damage/weak joints. #### Encapsulation - **Definition:** Enclosing semiconductor die, bond wires, and internal components within a protective material (plastic/ceramic). - **Purpose:** Protects from moisture, dust, contaminants, mechanical damage; provides electrical insulation; improves reliability/durability. - **Key Techniques:** 1. **Transfer Molding:** Most common, epoxy molding compound heated and transferred into mold cavity. 2. **Compression Molding:** Molding compound directly compressed over device (better for advanced packages). 3. **Glob Top Encapsulation:** Epoxy resin dispensed as a drop over the chip (used in Chip-on-Board). 4. **Dam and Fill Process:** Dam created around chip, then filled with encapsulant (for fine-pitch devices). 5. **Underfill Encapsulation:** Epoxy filled between die and substrate (improves mechanical strength/thermal cycling). 6. **Hermetic Sealing:** Airtight sealed package (high reliability, military/aerospace). ### Reliability Testing & Substrate Technology #### Reliability Testing Overview - **Definition:** Evaluating how well a device or system performs over time under specified conditions, without failure. - **Why Needed:** Ensure long-term performance, predict failure rate/lifetime, improve product quality, detect weaknesses. - **Bathtub Curve:** Represents failure rate vs. time: 1. **Infant Mortality (Early Failures):** High initial rate due to manufacturing defects (targeted by Burn-In). 2. **Useful Life (Random Failures):** Low, constant failure rate (normal operation). 3. **Wear-Out (Aging Failures):** Increasing failure rate due to aging effects (electromigration, oxide breakdown). #### Key Reliability Tests 1. **MSL (Moisture Sensitivity Level):** - **Definition:** Determines sensitivity to moisture absorption before solder reflow. - **Failures:** Popcorn cracking, delamination, wire bond damage due to moisture vaporization during reflow. - **Test Flow:** Electrical Test → CSAM → Dry Bake → Humidity Soak → Reflow → Electrical Test → CSAM. 2. **TC / TS (Temperature Cycling & Temperature Shock):** - **Definition:** Evaluates package robustness against thermal stress from repeated temperature changes. - **TC (Cycling):** Gradual cycling (e.g., $-40^\circ C$ to $+125^\circ C$), studies fatigue from CTE mismatch. - **TS (Shock):** Rapid transfer between hot/cold (e.g., $-65^\circ C$ to $+150^\circ C$), more severe. - **Failures:** Solder joint fatigue, die crack, wire bond lift, EMC crack, delamination. 3. **HAST / uHAST (Highly Accelerated Stress Test):** - **Definition:** Accelerates moisture penetration, corrosion, ionic contamination effects. - **HAST:** Uses high temperature, high humidity, pressure, and electrical bias. - **uHAST:** Unbiased HAST (no electrical bias), studies material moisture robustness. - **Failures:** Corrosion, leakage current, dendritic growth, passivation crack, wire bond corrosion. #### Substrate Technology - **Definition:** Mechanical base and electrical interconnection medium between IC die and PCB. - **Main Types:** Ceramic, Organic, Leadframe. | Property | Ceramic | Organic | Leadframe | |-----------------------|--------------|----------------|--------------| | **Cost** | High | Low | Lowest | | **Thermal Conductivity** | Excellent | Moderate | Good | | **Electrical Performance** | Excellent | Good | Moderate | | **Mechanical Strength** | Brittle | Flexible | Strong | | **High Frequency Usage** | Excellent | Good | Limited | | **Packaging Complexity** | High | High | Simple | | **Typical Packages** | RF/Military | BGA/FCBGA | QFN/QFP/SOP | - **Reliability Concerns:** - **Ceramic:** Brittle fracture, high cost. - **Organic:** Moisture absorption, warpage, delamination. - **Leadframe:** Lead fatigue, corrosion, oxidation. - **CTE Comparison (Approx):** Silicon: ~3 ppm/$^\circ C$; Ceramic: ~5–7 ppm/$^\circ C$; Organic: ~15–20 ppm/$^\circ C$; Copper Leadframe: ~17 ppm/$^\circ C$. Lower mismatch = better reliability. #### Die Attach Film (DAF) - **Definition:** Polymer-based adhesive film to bond die to substrate, replacing paste. - **Functions:** Strong adhesion, thermal/electrical conduction, reduces thickness, controls die movement, enhances reliability. - **Advantages:** Eliminates dispensing process, precise packaging, thin bondline, ambient storage, improved footprint, thermal/electrical conductivity. - **Types:** Normal DAF (standard bonding), FOW (Film Over Wire, wire protection), FOD (Film Over Die, die covering), Conductive DAF (heat/electrical conduction). ### Failure Analysis & Quality Control #### FA Flow – Basic Process (EFA to PFA) Systematic process to identify what, where, why a device failed, its root cause, and corrective action. 1. **Failure Occurrence** 2. **Electrical Failure Analysis (EFA):** Verify failure, identify mode, narrow defect area. 3. **Visual Inspection:** Detect visible defects (non-destructive). 4. **Fault Isolation (FI):** Pinpoint exact defect location (non-destructive). 5. **Physical Failure Analysis (PFA):** Physically expose/observe defect (destructive). 6. **Root Cause Identification** 7. **Corrective Action & Report** #### Important FA Terminologies - **Failure Mode:** How the device fails electrically (e.g., excessive current, open circuit, leakage). - **Failure Mechanism:** Physical reason behind failure (e.g., corrosion, electromigration, die crack). - **Root Cause:** Actual origin of failure (e.g., improper molding temperature, poor bonding parameter). #### Electrical Failure Analysis (EFA) - **Purpose:** Verify true failure, identify electrical failure mode, narrow defect area, guide next FA step. - **Tools:** - **ATE (Automated Test Equipment):** Functional, parametric, leakage, timing tests. - **Bench Testing:** Characterizes device using power supply, oscilloscope, multimeter, curve tracer. - **IV Curve Tracing:** Measures Current-Voltage characteristics to compare good vs. failed units. - **Open Failure:** Current $\approx 0$, very high resistance (broken wirebond, cracked trace). - **Short Failure:** Voltage $\approx 0$, very high current (metal/solder bridge, EOS damage). - **Leakage Failure:** Small abnormal current (junction damage, contamination, moisture). - **High Resistance Failure:** Reduced IV slope (poor solder joint, partial crack). #### Non-Destructive FA Tools - **Optical Microscope (OM):** Uses visible light to magnify surface. Detects package cracks, missing solder balls, scratches, wire damage, EOS marks. - **SAM (Scanning Acoustic Microscopy):** Uses ultrasonic waves. Detects delamination, voids, die cracks, EMC cracks. - **2D X-Ray:** X-rays pass through package, forms 2D grayscale image. Detects broken wirebonds, solder voids, missing solder balls, bridge defects, Cu trace cracks. - **3D X-Ray (CT):** Multiple 2D X-ray images for 3D volumetric model. Provides depth information, layer-by-layer analysis. Detects non-wet solder, internal shorts, via cracks, Cu migration, delamination. #### Destructive FA Tools - **Decapsulation:** Removes mold compound (acid etching, laser) to expose die, wirebond, bond pads. Detects EOS damage, die cracks, bond corrosion. - **Cross-Sectioning:** Mechanical cutting/polishing to expose internal plane. Detects solder cracks, Cu migration, voids, non-wet issues, delamination. - **FIB (Focused Ion Beam):** Uses Gallium ion beam for nano cross-section, precision milling, defect localization. Detects via cracks, EOS, delamination, die defects. - **SEM (Scanning Electron Microscope):** Electron beam scans surface for high magnification images. Applications: fracture/crack analysis, surface morphology. - **EDX (Energy Dispersive X-Ray):** Measures X-rays emitted for elemental composition. Detects Cu, Sn, Au contamination. #### ESD Management - **Definition:** Electrostatic Discharge (ESD) is sudden charge transfer between objects. Damages ICs (thin oxide, small geometries). - **Causes:** Triboelectric effect (friction), Human Body Charging (capacitive discharge), Insulators (charge accumulation), Low Humidity. - **Failure Mechanisms:** Gate oxide breakdown, junction damage, metal melting, short circuit, leakage, latent failure. - **Models:** HBM (Human Body Model), MM (Machine Model), CDM (Charged Device Model). - **Prevention Methods:** Grounding (wrist straps, ESD flooring), Ionizers (neutralize charges), Humidity Control, ESD-Safe Packaging. - **ESD vs. EOS:** ESD is very short, static discharge, lower energy, localized damage. EOS (Electrical Overstress) is longer, electrical overstress, higher energy, severe melting/burning. ### Quality Management & Process Control #### Quality Management (QM) - **Definition:** Systematic process to ensure products consistently meet quality standards. - **Objectives:** High reliability, low defect rate, customer satisfaction, standards compliance, continuous improvement. - **Components:** Quality Planning, Quality Assurance (QA - proactive), Quality Control (QC - reactive), Continuous Improvement. #### Cost of Quality (CoQ) - **Definition:** Total cost incurred to ensure good quality and cost arising from poor quality. - **Categories:** 1. **Prevention Cost (CoP):** Costs to prevent defects (e.g., employee training, process design, ATE calibration). *Most desirable.* 2. **Appraisal Cost (CoA):** Costs to detect defects (e.g., inspection, electrical testing, Burn-In, X-ray, SAM). 3. **Internal Failure Cost (CoIF):** Costs for defects BEFORE shipment (e.g., scrap, rework, retesting). 4. **External Failure Cost (CoEF):** Costs for defects AFTER shipment (e.g., warranty claims, product recall, customer complaints). *Most dangerous/expensive.* - **Formula:** $CoQ = CoP + CoA + CoIF + CoEF$ - **Industrial Goal:** Higher CoP, lower CoIF/CoEF. #### FMEA (Failure Mode and Effects Analysis) - **Definition:** Systematic risk analysis to identify possible failures, causes, effects, and preventive actions. - **Types:** - **D-FMEA (Design FMEA):** Analyzes failures from product design, material selection, architecture. Focus: "What can fail in the DESIGN?" - **P-FMEA (Process FMEA):** Analyzes failures during manufacturing, assembly, testing. Focus: "What can fail in the MANUFACTURING PROCESS?" - **Risk Priority Number (RPN):** $RPN = S \times O \times D$ - **S (Severity):** Seriousness of effect (1-10). - **O (Occurrence):** Probability of failure (1-10). - **D (Detection):** Ability to detect failure (1-10). - Higher RPN = Higher risk, requires immediate action. #### Statistical Process Control (SPC) - **Definition:** Statistical methods to monitor and control a process for consistent quality. - **Why Important:** Millions of devices, tiny variations, manual monitoring impossible. - **Variation Types:** - **Common Cause Variation:** Natural/random, stable, predictable (e.g., minor temp fluctuation). - **Special Cause Variation:** Abnormal/unexpected, unstable, requires correction (e.g., machine failure, contamination). - **Control Chart:** Graph showing process data, mean line, Upper Control Limit (UCL), Lower Control Limit (LCL). Detects process abnormality (out-of-control conditions = special cause variation). - **Process Capability (Cp, Cpk):** Measures ability of process to meet specifications. #### Measurement System Analysis (MSA) - **Definition:** Statistical method to evaluate accuracy, precision, stability, reliability of a measurement system. - **Why Important:** Semiconductor measurements are sensitive, small tolerances; wrong data leads to bad decisions. - **Concepts:** - **Accuracy:** Closeness to true value. - **Precision:** Consistency of repeated measurements. - **Repeatability (EV):** Variation when same operator/instrument/method measures same part repeatedly. - **Reproducibility (AV):** Variation caused by different operators. - **Stability:** Consistent performance over time. - **Bias:** Difference between measured and true value. - **Gauge R&R:** Evaluates repeatability and reproducibility ($GR\&R = EV + AV$). #### Fault Detection Control (FDC) - **Definition:** Real-time monitoring and control system to detect process abnormalities before defects are produced. - **Need:** Highly automated, sensitive, high-speed, precision-dependent processes. - **Basic Concept:** Continuously monitors sensors, parameters, signals; compares with control limits/models. If abnormality, alarms, stops tool, engineer notified. #### Run-to-Run Control (R2R) - **Definition:** Automatic feedback control system that adjusts process parameters between runs based on previous run results. - **Why Needed:** Compensate for tool drift, material variation, environmental changes, equipment aging. - **Main Objective:** Reduce process variation, keep output close to target. - **EWMA Controller:** Common algorithm, Exponentially Weighted Moving Average, smooths noise, tracks drift. #### Incoming Material Inspection (IMI) - **Definition:** Inspecting raw materials, components, consumables before manufacturing. - **Purpose:** Verify material quality, prevent defective material usage, improve yield/reliability. - **Types:** Visual, Dimensional, Electrical, Chemical, Reliability Qualification. #### In-Line Quality - **Definition:** Continuous monitoring and inspection during manufacturing processes in real time. - **Objectives:** Detect defects early, prevent propagation, improve process control, reduce scrap/rework, improve yield. - **Methods:** Visual, AOI (Automated Optical Inspection), X-ray, SPC, FDC, Electrical Testing. #### Auto Defect Classification (ADC) - **Definition:** Automated inspection system using image processing, pattern recognition, AI/ML to detect and classify defects. - **Need:** Millions of devices, tiny features, huge data, manual inspection is slow/inconsistent. - **Benefits:** Faster, better accuracy, continuous monitoring, reduced labor, better yield analysis. #### Machine Communication Protocol - **Definition:** Standardized method for data exchange and equipment communication between manufacturing machines and computer systems. - **Need:** Automation, data integration, smart manufacturing. - **Protocols:** SECS/GEM (most important semiconductor protocol), OPC-UA, MQTT.