Three input cmos logic gate — Free Electronics Illustration | GPAI | GPAI

gpai

Terms of Service Privacy Policy

© 2026 Turing Co., Ltd. All rights reserved.

Three input cmos logic gate — Free Electronics Illustration | GPAI | GPAI

Library
/
Electronics
/
Three input cmos logic gate

Three input cmos logic gate

Electronics

Three input cmos logic gate

A CMOS logic gate schematic with a pull-up network of three PMOS transistors near the top tied to a VDD rail and a pull-down network of three NMOS transistors near the bottom tied to ground, both connected to a central output node labeled Y. Three input lines labeled A, B, and C connect to matching transistor gates.

Edit this icon in GPAI Canvas — mix it with 80,000+ STEM assets and AI editing tools to ship publication-ready figures in minutes

Format

PNG

License

More electronics illustrations

Integrated circuit chip quad flat package

Integrated circuit chip quad flat package

Driver transistor q2

Driver transistor q2

Lc resonator

Capacitor cpi

Emitter follower output stage

Emitter follower output stage

Harmonic distortion spectrum

Harmonic distortion spectrum

Interconnect wire

Interconnect wire

Three stage amplifier transistor circuit

Three stage amplifier transistor circuit