Latch type sense amplifier — Free Electronics Illustration | GPAI

Electronics

Latch type sense amplifier

A symmetric latch-type sense amplifier drawn explicitly as a transistor-level CMOS schematic. Two mirrored MOSFET branches face each other in a cross-coupled structure, typically using paired PMOS and NMOS devices or cross-coupled CMOS inverters. The schematic includes a top VDD rail and a bottom ground rail or tail current source, with opposite differential input/output nodes associated with complementary bit lines. Active-load devices may appear above the central matched transistors. The entire circuit is strongly left-right mirrored, rendered with thin black schematic lines and clearly labeled terminals.

Edit this icon in GPAI Canvas — mix it with 80,000+ STEM assets and AI editing tools to ship publication-ready figures in minutes