Cmos inverter — Free Electronics Illustration | GPAI

Electronics

Cmos inverter

Standard transistor-level CMOS inverter schematic drawn in clean black circuit-diagram line art on a white background. A p-channel MOSFET is stacked vertically above an n-channel MOSFET between a top positive supply rail labeled VDD and a bottom ground rail. The PMOS source connects to VDD and the NMOS source connects to ground. Both transistor gates are tied together to a single input node on the left, and the two drains are joined to form a single shared output node on the right. Use conventional MOSFET symbols with clear source, drain, and gate terminals; the PMOS may be marked with a small gate bubble while the NMOS has no bubble. Overall appearance is a compact vertical pull-up/pull-down inverter stage with straight, simple connection lines.

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