Domino cmos logic gate — Free Electronics Illustration | GPAI

Electronics

Domino cmos logic gate

Schematic transistor-level diagram of a Domino CMOS logic gate. A dynamic logic stage on the left feeds a static CMOS inverter on the right. The dynamic stage includes a clocked pMOS precharge transistor at the top connected to VDD, an internal dynamic node labeled X with a load capacitor, and an nMOS pull-down evaluation network stacked to ground. The node X connects directly to a standard CMOS inverter drawn with a pMOS transistor above an nMOS transistor, and the inverter output is labeled Y. Clean black line-art schematic style with a clear precharge/evaluate structure and a single output node.

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