Pun series two pmos — Free Electronics Illustration | GPAI | GPAI

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Pun series two pmos — Free Electronics Illustration | GPAI | GPAI

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Pun series two pmos

Pun series two pmos

Electronics

Pun series two pmos

A pull-up network schematic consisting of two PMOS transistors connected in series between a VDD rail at the top and an output node Y at the bottom. The upper transistor gate is labeled A and the lower transistor gate is labeled B, with gate bubbles indicating PMOS devices.

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