Three input nor gate cmos — Free Electronics Illustration | GPAI | GPAI

gpai

Terms of Service Privacy Policy

© 2026 Turing Co., Ltd. All rights reserved.

Three input nor gate cmos — Free Electronics Illustration | GPAI | GPAI

Library
/
Electronics
/
Three input nor gate cmos

Three input nor gate cmos

Electronics

Three input nor gate cmos

A transistor-level CMOS four-input NOR gate schematic with four PMOS transistors connected in series in the pull-up network and four NMOS transistors connected in parallel in the pull-down network. Inputs labeled A, B, C, and D control paired transistors, with output Y at the joined center node and VDD rail at the top.

Edit this icon in GPAI Canvas — mix it with 80,000+ STEM assets and AI editing tools to ship publication-ready figures in minutes

Format

PNG

License

More electronics illustrations

Delay block

Common emitter amplifier

Common emitter amplifier

Chassis

Resistor zigzag

Resistor zigzag

Pole at infinity

Pole at infinity

Thevenin resistance

Thevenin resistance

Input stage op amp

Input stage op amp

Peak clipping waveform

Peak clipping waveform