Pseudo nmos nor gate — Free Electronics Illustration | GPAI | GPAI

gpai

Terms of Service Privacy Policy

© 2026 Turing Co., Ltd. All rights reserved.

Pseudo nmos nor gate — Free Electronics Illustration | GPAI | GPAI

Library
/
Electronics
/
Pseudo nmos nor gate

Pseudo nmos nor gate

Electronics

Pseudo nmos nor gate

Schematic-style four-input pseudo-NMOS NOR gate with a single PMOS load transistor at the top connected to VDD and four separate NMOS transistors below connected in parallel to ground. A single output node labeled Y is shared between the PMOS and the NMOS pull-down network. The PMOS is drawn with a gate tied low, and the four NMOS devices are labeled by inputs A, B, C, and D.

Edit this icon in GPAI Canvas — mix it with 80,000+ STEM assets and AI editing tools to ship publication-ready figures in minutes

Format

PNG

License

More electronics illustrations

Chip io data line

Chip io data line

Output equivalent circuit

Output equivalent circuit

Sige wafer

3v supply

Square wave output voltage

Square wave output voltage

Base resistor rx

Base resistor rx

Bit line bar

Physically implanted channel

Physically implanted channel