Embedded Systems Essentials

Cheatsheet Content

Embedded Systems Overview Definition: Computer system physically "embedded" in its environment, often controlling it. Characteristics: Single-functioned, customized microprocessor for specific program/purpose. Reactive, continually responds to environment changes. Operates under tight constraints, requires "Real Time" results. Embodied Phenomena: Systems coexist to discharge a specific function in real time and real space. Microprocessor vs. Microcontroller Feature Microprocessor Microcontroller Definition CPU core, needs external components (RAM, ROM, I/O) CPU, RAM, ROM, Timer, ADC, Serial Ports all on one chip Application Desktop computers, high-performance systems Embedded systems (washing machines, toys, automobiles) Complexity 32-bit or 64-bit, designed for high performance Simpler, often 8-bit, designed for power efficiency Memory Complex memory hierarchy, often with cache Simpler memory hierarchy, often no cache Cost/Vol. Expensive, lower volume Cost-sensitive, highest volume processors Memory Types: ROM vs. RAM ROM (Read-Only Memory) Function: Stores software programs or constant data that doesn't change. Structure: Grid system with decoder to find data based on address. Analogy: Like a printed textbook (read-only). Types: Standard ROM: Fixed data or logic functions. EPROM (Erasable Programmable ROM): Can be erased (UV light, 5-30 min) and rewritten. Uses "floating gate" technology. EEPROM/Flash: Mentioned in context of NVRAM (paired with SRAM). RAM (Random Access Memory) Function: Volatile memory; loses data when power is off. Allows easy read/write during execution. Structure: Grid where each cell connects to a Read/Write line. More complex than ROM. Types: SRAM (Static RAM): Each cell uses a flip-flop (6 transistors). Holds data as long as power is supplied. Faster, less compact, more expensive than DRAM. Used for cache memory. DRAM (Dynamic RAM): Each cell uses 1 MOS transistor and a capacitor. More compact, but slower than SRAM. Requires "Refresh" cycle (e.g., every $15.625 \mu s$) due to capacitor charge leakage. Variations: FPM DRAM (Fast Page Mode): Reads multiple words consecutively from same row (page). EDO RAM (Extended Data Out): Overlaps control signal strobing with data read, reducing latency. SDRAM (Synchronous DRAM): Latches data on system clock edge, uses internal counter for consecutive access. ESDRAM (Enhanced SDRAM): Adds buffers for overlapping column addressing, faster clocking. PSRAM (Pseudo-static RAM): DRAM with a built-in memory refresh controller. Behaves like SRAM externally, but uses DRAM internally. Low-cost, high-density alternative to SRAM. NVRAM (Nonvolatile RAM): Holds data after power removal. Battery-backed RAM: SRAM + battery. Unlimited fast reads/writes. SRAM with EEPROM/Flash: RAM contents stored to non-volatile memory before power loss. Cache Memory Definition: High-speed memory (usually SRAM) on the processor chip. Smaller than main memory but much faster (1 cycle vs. several). Operation: Request: System checks cache first for main memory access. Cache Hit: Data found in cache, quick access. Cache Miss: Data not found, read from main memory into cache. Cache Line: Indivisible blocks (4 or 8 adjacent addresses) for data transfer. Cache Mapping Techniques Purpose: Assign main memory address to cache address and detect hit/miss. 1. Direct Mapping: Main memory address divided into: Index: Cache address. Tag: Compared with tag in cache. Offset: Word within cache line. Valid Bit: Indicates if data slot is loaded from memory. 2. Fully Associative Mapping: Complete main memory address stored in each cache address. Unlike direct mapping, no specific index restriction; all addresses simultaneously compared. Uses Valid bit and Offset. 3. Set-Associative Mapping: Hybrid: Index points to a set, multiple tags compared within the set. Performance improves with increased associativity. Processor Classes 1. General Purpose - High Performance: Usage: General-purpose software (e.g., workstations, PCs). OS: "Heavy weight" (UNIX, NT). Examples: Pentiums, Alpha's, SPARC. 2. Embedded Processors & Processor Cores: Usage: Single program (e.g., cellular phones, CD players). OS: Lightweight, real-time operating systems (RTOS). Features: Often include DSP support. Examples: ARM, 486SX, Hitachi SH7000. 3. Microcontrollers: Characteristics: Extremely cost-sensitive, highest volume. Architecture: Small word size (e.g., 8-bit). Applications: Everyday appliances (automobiles, toasters). Digital Signal Processor (DSP) Definition: Electronic system that processes digital signals. Function: Applies mathematical operations to digitally represented signals (sequences of samples from ADC). Tasks (Real-time): Signal Modeling: Convolution, transfer functions, frequency response. Signal Processing: Filtering, estimation, algorithms, data manipulation. Design Constraints: Minimize cost, power, memory, development time. System Requirements: Repetitive numeric computations, strict numeric fidelity, high memory bandwidth (array access). Finite Impulse Response (FIR) Filter Definition: Digital filter where output is linear combination of present and past input values. Mathematical Representation: $y(k) = \sum_{i=0}^{N-1} h_i x(k-i)$ $y(k)$: output, $x(k)$: input, $h_i$: filter coefficients. Advantages: Linear phase, stability, improved computational time. Intel 8XC196 Microcontroller Architecture Highly integrated: Designed for embedded control applications. Core Components: Register File: Register RAM, CPU Special Function Registers (SFRs). RALU (Register ALU): ALU, Microcode Engine, Master Program Counter (PC), Program Status Word (PSW). Memory Controller: Prefetch Queue, Slave PC, Bus Controller. On-Chip Peripherals: Signal Processing: A/D, PWM, WG (Waveform Generator), FG (Frequency Generator). Control & Timing: EPA (Event Processor Array), WDT (Watchdog Timer). Communication: SIO (Serial I/O), general-purpose I/O ports. System Management: Clock/Power Management, Interrupt Controller, PTS (Peripheral Transaction Server), optional on-chip ROM. Power Supply to Multiple Points in Chips 1. Voltage Stability & Correct Operation: Ensures voltages at individual devices remain at/above target. Guarantees circuits operate correctly under varying load conditions. 2. Current Management & Distribution: Keeps current from a single pad/pin/regulator within safety limits. Prevents overload of regulators and pads. Minimizes noise (Ldi/dt variations) by distributing currents uniformly. Time-Multiplexed Data Transfer Technique: Transmits multiple pieces of information over same physical wires by separating them in time. Requires a multiplexer (mux) at transmitter (Master) and demultiplexer (demux) at receiver (Servant). Applications: 1. Data Serializing (Reducing Wire Count): Example: Transmitting 16 bits over an 8-bit line. Process: MSB (15:8) sent first, then LSB (7:0). 2. Address/Data Muxing (Sharing Functionality): Same wires carry Address first, then Data. Synchronization: Uses a control signal (e.g., 'req') to distinguish time slots (e.g., MSB vs. LSB, Address vs. Data). Difference Between Strobe and Handshake Protocol Feature Strobe Protocol Handshake Protocol Basic Concept Unilateral method where the Master initiates transfer without waiting for a response from the Servant. Bilateral method where the Master and Servant exchange signals to coordinate the transfer. Control Signals Uses a single control signal: req (Request). Uses two control signals: req (Request) and ack (Acknowledge). Feedback Mechanism No feedback. The Master assumes the Servant is ready and has captured the data. Explicit feedback. The Servant sends an ack signal to confirm it is ready or has received the data. Sequence of Operation Master asserts req . Data is transferred. Master de-asserts req . Master asserts req . Servant asserts ack . Master de-asserts req . Servant de-asserts ack . Synchronization Asynchronous but relies on fixed timing; the Master does not know if the Servant is actually ready. Fully synchronized; the Master waits for the ack signal before proceeding to complete the cycle. Reliability Faster but less reliable if the Servant is slower than the Master. More reliable as it accommodates devices of different speeds, though it requires more steps. Comparison: RTES I/O vs. PC I/O Feature RTES I/O (Real-Time Embedded System I/O) PC I/O (Personal Computer I/O) Timing Requirements Must operate in real-time. Strict timing requirements must be met. Can take longer to respond. Generally no stringent timing requirements. Nature of Devices Often not for human users; analog interfaces, digital controllers, mixed-signal circuits for machine interaction. Primarily for human users; keypads, monitors, mice (can also include RTES-like I/Os). Power Consumption Strictly limited; often battery-operated or energy-constrained. Virtually no strict limit on power consumption. Size Constraints Devices must be small to coexist efficiently within a compact space. Size is generally not a problem; desktop PCs are not designed for portability like embedded devices.