VHDL Golden Reference

Cheatsheet Content

### Introduction to VHDL - **VHDL** (VHSIC Hardware Description Language) is a standard language for describing digital electronic circuits and systems. - It's used for simulation, synthesis, and verification of hardware designs. - **VHSIC** stands for Very High Speed Integrated Circuit. ### Basic Structure A VHDL design typically consists of two main parts: 1. **Entity:** Defines the interface (ports) of the hardware module. 2. **Architecture:** Describes the internal behavior or structure of the module. ```vhdl -- Library declaration library ieee; use ieee.std_logic_1164.all; -- Entity declaration entity my_gate is port ( a_in : in std_logic; b_in : in std_logic; c_out : out std_logic ); end entity my_gate; -- Architecture declaration architecture behavioral of my_gate is begin c_out ### Data Types | Type | Description | Examples | | :----------------- | :--------------------------------------------- | :------------------------ | | `std_logic` | 9-state logic value (U, X, 0, 1, Z, W, L, H, -) | `'0'`, `'1'`, `'Z'` | | `std_logic_vector` | Array of `std_logic` | `std_logic_vector(7 downto 0)` | | `bit` | 2-state logic value ('0', '1') | `'0'`, `'1'` | | `bit_vector` | Array of `bit` | `bit_vector(3 to 0)` | | `integer` | Integer numbers | `0`, `100`, `-5` | | `natural` | Non-negative integers (`0` to `integer'high`) | `0`, `10`, `1000` | | `positive` | Positive integers (`1` to `integer'high`) | `1`, `5`, `200` | | `boolean` | `TRUE` or `FALSE` | `TRUE`, `FALSE` | | `real` | Floating-point numbers (for simulation only) | `3.14`, `1.0E-9` | | `time` | Physical type for time (for simulation only) | `10 ns`, `500 ps` | ### Operators - **Logical:** `and`, `or`, `nand`, `nor`, `xor`, `xnor`, `not` - **Relational:** `=`, `/=`, ` `, `>=` - **Arithmetic:** `+`, `-`, `*`, `/`, `mod`, `rem`, `abs`, `**` (power) - **Concatenation:** `&` (e.g., `"00" & '1'` results in `"001"`) - **Shift (IEEE.NUMERIC_STD):** `sll`, `srl`, `sla`, `sra`, `rol`, `ror` ### Concurrent Statements Statements that execute in parallel. #### Signal Assignment ```vhdl signal_a main_sig_a, sub_out1 => main_sig_b ); ``` ### Sequential Statements Statements that execute in order within a `process` block. #### Process ```vhdl process (clk, reset) begin if reset = '1' then count '0'); elsif rising_edge(clk) then count next_state next_state next_state ### Packages Used to group common declarations (types, constants, functions, procedures). - `IEEE.STD_LOGIC_1164`: Defines `std_logic` and `std_logic_vector`. - `IEEE.NUMERIC_STD`: Defines arithmetic operations for `std_logic_vector` (using `unsigned` and `signed` types). - `IEEE.STD_LOGIC_UNSIGNED`, `IEEE.STD_LOGIC_SIGNED`: (Non-standard, avoid for new designs) Provide similar functionality to `NUMERIC_STD` but implicitly convert. ```vhdl library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- For signed/unsigned arithmetic package my_utils is constant DATA_WIDTH : integer := 8; function increment (val : unsigned) return unsigned; end package my_utils; package body my_utils is function increment (val : unsigned) return unsigned is begin return val + 1; end function; end package body my_utils; ``` ### Common Design Patterns #### Flip-Flop (D-Type) ```vhdl process (clk, reset) begin if reset = '1' then q '0'); elsif rising_edge(clk) then if enable = '1' then q if some_condition then next_state -- ... when others => next_state output_signal output_signal output_signal ### Configuration Used to bind an entity to a specific architecture, or to bind components to specific entities/architectures. ```vhdl configuration my_design_cfg of top_entity is for behavioral for U1 : my_sub_module use entity work.my_sub_module(rtl); -- Binds U1 instance to rtl architecture end for; end for; end configuration my_design_cfg; ``` ### Generics Parameters that can be passed to an entity to customize its behavior or structure (e.g., data width, buffer size). ```vhdl entity generic_adder is generic ( N : integer := 8 -- Default width is 8 bits ); port ( a_in : in std_logic_vector(N-1 downto 0); b_in : in std_logic_vector(N-1 downto 0); sum_out : out std_logic_vector(N-1 downto 0) ); end entity generic_adder; architecture rtl of generic_adder is begin sum_out 8) port map ( a_in => data_a, b_in => data_b, sum_out => result_sum ); ``` ### Attributes Used to provide additional information about a design element or to control synthesis/simulation tools. ```vhdl -- Example: To specify a state encoding for FSMs type state_type is (IDLE, S1, S2); attribute enum_encoding : string; attribute enum_encoding of state_type : type is "00 01 10"; -- Example: To mark a signal as a clock for synthesis tools signal clk : std_logic; attribute syn_is_clock : boolean; attribute syn_is_clock of clk : signal is true; ```