Digital Electronics Post-Midsem

Cheatsheet Content

Sequential Logic Fundamentals Flip-flops Definition: A bistable multivibrator that can store one bit of information. Types: SR Flip-Flop: Set-Reset. Inputs: S (Set), R (Reset) Output: Q, Q' Truth Table: S R Q$_{next}$ State 0 0 Q$_{prev}$ Hold 0 1 0 Reset 1 0 1 Set 1 1 Invalid Forbidden D Flip-Flop: Data or Delay. Inputs: D (Data), Clock (Clk) Output: Q, Q' Truth Table: Clk D Q$_{next}$ $\uparrow$ 0 0 $\uparrow$ 1 1 0/1 X Q$_{prev}$ Used for storing data, registers. JK Flip-Flop: Universal flip-flop. Inputs: J, K, Clock (Clk) Output: Q, Q' Truth Table: Clk J K Q$_{next}$ $\uparrow$ 0 0 Q$_{prev}$ $\uparrow$ 0 1 0 $\uparrow$ 1 0 1 $\uparrow$ 1 1 Q'$_{prev}$ Can be configured as SR, D, or T flip-flops. T Flip-Flop: Toggle. Inputs: T (Toggle), Clock (Clk) Output: Q, Q' Truth Table: Clk T Q$_{next}$ $\uparrow$ 0 Q$_{prev}$ $\uparrow$ 1 Q'$_{prev}$ Used in counters. Latches Definition: Level-sensitive memory elements. Output can change as long as the enable signal is active. Difference from Flip-flops: Latches are level-triggered, Flip-flops are edge-triggered. Types: SR Latch (NAND/NOR based): No clock input, asynchronous. Gated D Latch: Has an enable input. Output follows input D when enable is high. Clocked Sequential Circuits Definition: Circuits where state changes are synchronized by a clock signal. Components: Flip-flops (memory elements) and combinational logic. Synchronous vs. Asynchronous: Synchronous: All flip-flops are triggered by the same clock edge. Asynchronous: Flip-flops are triggered at different times or by different clocks/events. Analysis of Clocked Circuits Steps: From the circuit diagram, derive excitation equations for each flip-flop input. Derive output equations for the circuit. Substitute excitation equations into the flip-flop characteristic equations to get state equations. Construct the state table (present state, inputs, next state, outputs). Draw the state diagram. Flip-flop Characteristic Equations: SR: $Q_{next} = S + R'Q$ (where $SR=0$) D: $Q_{next} = D$ JK: $Q_{next} = JQ' + K'Q$ T: $Q_{next} = TQ' + T'Q = T \oplus Q$ State Diagrams and Reduction State Diagram: Graphical representation of a sequential circuit's behavior. Nodes are states, directed edges are transitions, labeled with Input/Output. State Table: Tabular representation of state transitions and outputs. State Reduction: Process of minimizing the number of states in a sequential circuit while preserving its input/output behavior. Why: Reduces hardware complexity (fewer flip-flops). Methods: Implication Table Method: Create a table comparing all pairs of states. Mark incompatible pairs (different outputs for the same input). Identify implied states for compatible pairs. Iteratively eliminate incompatible pairs. Find maximal compatible sets. Select minimal set of maximal compatibles to cover all states. Partitioning Method: Grouping states into equivalence classes. Registers and Counters Registers Definition: A group of flip-flops used to store multiple bits of binary data. Types: Parallel Load Registers: All bits are loaded simultaneously. Shift Registers: Bits are shifted sequentially. SIPO (Serial-In, Parallel-Out): Data enters serially, read out in parallel. PISO (Parallel-In, Serial-Out): Data enters in parallel, read out serially. SISO (Serial-In, Serial-Out): Data enters and exits serially. PIPO (Parallel-In, Parallel-Out): Data enters and exits in parallel. Universal Shift Register: Can perform multiple shift operations (right, left, parallel load, hold) based on control inputs. Counters Definition: A sequential circuit that cycles through a predefined sequence of states. Types: Asynchronous (Ripple) Counters: Flip-flops are clocked by the output of the preceding flip-flop. Simpler to design. Propagation delay accumulates, limiting speed. Example: Ripple Up Counter, Ripple Down Counter. Synchronous Counters: All flip-flops are clocked simultaneously by a common clock signal. More complex design (requires combinational logic for J/K/T inputs). Higher speed due to simultaneous state changes. Example: Synchronous Up Counter, Synchronous Down Counter, Ring Counter, Johnson Counter. Modulus (MOD) of a Counter: The number of distinct states the counter passes through. An $n$-bit counter has a maximum MOD of $2^n$. Design Procedure for Synchronous Counters: State Diagram/Sequence. State Table. Flip-flop Excitation Table (for chosen FF type: D, JK, T). K-maps for each flip-flop input and output. Draw the circuit diagram. Design of Asynchronous Circuits Definition: Sequential circuits where state changes occur based on changes in input signals without a global clock. Challenges: Races: Multiple state variables changing simultaneously. Noncritical Race: Final stable state is independent of the order of changes. Critical Race: Final stable state depends on the order of changes (must be avoided). Hazards: Transient glitches in the output due to unequal propagation delays. Static Hazard: Output momentarily goes to 0 when it should stay 1 (static-1 hazard) or momentarily goes to 1 when it should stay 0 (static-0 hazard). Dynamic Hazard: Output changes more than once when it should change only once. Asynchronous Sequential Logic Design Flow Table: A table similar to a state table but explicitly showing stable and unstable states. Stable State: Present state equals next state. Represented by circled entries. Unstable State: Present state does not equal next state, indicating a transition. Primitive Flow Table: A flow table with only one stable state per row. Steps for Design: Obtain a primitive flow table from the problem statement. Reduce the flow table (merge rows using implication table). Assign binary codes to states (state assignment). This is critical to avoid critical races. Race-Free Assignment: Adjacent states in the flow table (differ by one input) should be assigned codes that differ in only one bit (unit distance codes). Derive transition and output functions. Implement the circuit using logic gates (latches or feedback loops). Hazard-Free Design: Add redundant prime implicants to cover all possible transitions in a K-map. For static-1 hazards, cover all adjacent pairs of 1s with a common product term. Memory and Programmable Logic Devices (PLD) Memory RAM (Random Access Memory): Volatile: Loses data when power is off. Read/Write: Data can be both read from and written to. Access Time: Independent of memory location. Types: SRAM (Static RAM): Uses latches (flip-flops) to store bits. Faster, more expensive, used for cache. DRAM (Dynamic RAM): Uses capacitors to store bits. Slower, cheaper, higher density, used for main memory. Requires periodic refreshing. ROM (Read Only Memory): Non-Volatile: Retains data without power. Read Only: Data is pre-programmed and cannot be easily changed. Types: Mask ROM (MROM): Programmed during manufacturing. PROM (Programmable ROM): User programmable once by blowing fuses. EPROM (Erasable PROM): Erasable by UV light, then reprogrammable. EEPROM (Electrically Erasable PROM): Erasable and reprogrammable electrically. Flash Memory: A type of EEPROM, block-erasable. Programmable Logic Devices (PLD) Definition: Integrated circuits with configurable logic gates and/or flip-flops, allowing users to implement custom digital circuits. Advantages: Flexibility, reduced board space, lower cost, faster design cycles. Types: PLA (Programmable Logic Array): Both AND array and OR array are programmable. More flexible than PAL, but more complex to program. Diagram: Inputs $\rightarrow$ Programmable AND array $\rightarrow$ Programmable OR array $\rightarrow$ Outputs. PAL (Programmable Array Logic): Programmable AND array, fixed OR array. Simpler to program than PLA, less flexible. Diagram: Inputs $\rightarrow$ Programmable AND array $\rightarrow$ Fixed OR array $\rightarrow$ Outputs. PROM (as PLD): Fixed AND array (decoder), programmable OR array. Primarily for implementing sum-of-minterms. Complex PLDs (CPLDs): Larger devices with multiple PAL-like blocks interconnected by a programmable switch matrix. Field-Programmable Gate Arrays (FPGAs): Most flexible and complex PLDs. Configurable logic blocks (CLBs), configurable I/O blocks (IOBs), and programmable interconnects. Used for high-performance and complex designs.